Data strobe for faster data access from a memory array

ABSTRACT

A memory subsystem for a computer system includes a memory controller that has a data strobe generator. The memory subsystem further includes a DRAM array coupled to the memory controller and a data path coupled to the data strobe generator and the DRAM array. The DRAM array is separated into two DRAM sets coupled to a common output bus. Access to the DRAM array begins with access to the first DRAM set. After a first CAS is applied to the first DRAM set, a data strobe is asserted which causes data from the first DRAM set to be latched into the data path. On the next clock cycle after the data strobe is asserted, the data strobe and first CAS are de-asserted. A second CAS is then applied to the second DRAM set on the next clock cycle after the first CAS is de-asserted.

FIELD OF THE INVENTION

[0001] The present invention is directed to accessing a memory array in a computer system. More particularly, the present invention is directed to accessing a memory array in a computer system using a data strobe.

BACKGROUND OF THE INVENTION

[0002] Computer systems require large amount of memory in order to store programs and data. One type of memory common to virtually all computer systems is dynamic random access memory (“DRAM”).

[0003] When accessing DRAM, a row address strobe (“RAS”) must first be asserted, and then a column address strobe (“CAS”) is asserted. Since DRAM is asynchronous, data cannot be read from or written into DRAM until some delay time after the CAS asserted, in order to allow the DRAM sufficient time to react to the CAS. This delay time reduces the access speed of the DRAM.

[0004] Another delay that reduces the access speed to DRAM is the time for the RAS and CAS signals to physically reach the DRAM after they are generated. In a typical desktop personal computer, the total DRAM might occupy 1-2 dual in-line memory module (“DIMM”) slots, and the signal delay is minimal. However, in large multiprocessor computer servers, the amount of required DRAM can sometimes occupy 32 or more DIMM slots. Because of the large number of memory boards in these systems, the longest trace lengths between the device generating the RAS and CAS signals and the DRAMs must be increased to reach all of the DRAMs. The increased trace length, because of added capacitance, further increases the time for the RAS and CAS signals to reach the DRAMs, therefore further reducing the access speed of the DRAMs.

[0005] Based on the foregoing, there is a need for a method and apparatus to increase the access speed of DRAM, regardless of the amount of DRAM in a computer system.

SUMMARY OF THE INVENTION

[0006] One embodiment of the present invention is a memory subsystem for a computer system. The memory subsystem includes a memory controller that has a data strobe generator. The memory subsystem further includes a DRAM array coupled to the memory controller and a data path coupled to the data strobe generator and the DRAM array.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007]FIG. 1 is a block diagram of a computer system in accordance with one embodiment of the present invention.

[0008]FIG. 2 is a block diagram illustrating in detail a memory controller, a DRAM memory array and a data path of a memory subsystem.

[0009]FIG. 3 is a timing diagram of DRAM access to the DRAM memory array of FIG. 2.

[0010]FIG. 4 is a block diagram illustrating in more detail the memory controller DRAM memory array and data path of the memory subsystem of FIG. 1 in accordance with one embodiment of the present invention.

[0011]FIG. 5 is a timing diagram of DRAM access to the DRAM memory array of FIG. 4.

DETAILED DESCRIPTION

[0012] One embodiment of the present invention is a data strobe between a memory controller and a data path to increase access speed to DRAM. Referring now in detail to the drawings, wherein like parts are designated by like reference numerals throughout, FIG. 1 is a block diagram of a computer system in accordance with one embodiment of the present invention.

[0013] Computer system 10 includes processors 20-23. In one embodiment. processors 20-23 are Pentium® II processors from Intel Corporation. Processors 2023 are coupled to a memory subsystem through a bus 25. The memory subsystem includes a memory controller 30, a DRAM memory array 40, and a data path 50.

[0014] DRAM memory array 40 comprises a plurality of DRAM. In one embodiment, the DRAM is packaged in DIMMs or single in-line memory modules (“SIMMs”). Further, in one embodiment the DRAM in DRAM memory array 40 is Extended Data Output (“EDO”) DRAM. In other embodiments, the DRAM in DRAM memory array 40 is fast page mode DRAM, synchronous DRAM, or any other type of DRAM.

[0015] Memory controller 30 is responsible for servicing requests for access to DRAM memory array 40 from other devices in computer system 10. Memory controller 30 includes state machines that output the required control signals used to access the DRAM in DRAM memory array 40. The control signals include RAS and CAS signals. Memory controller 30 further outputs a data strobe 55 signal to data path 50 that reduces overall access time for multiple accesses to DRAM memory array 40. In one embodiment, all outputs of memory controller 30 are generated by flip-flops that are clocked by the same clock signal and therefore are synchronous.

[0016] Data path 50 captures data from DRAM memory array 40 during a read operation (and vice versa during a write operation) and sends the data to the requesting device in computer system 10 over bus 25. In one embodiment, data path 50 comprises a plurality of multiplexers.

[0017]FIG. 2 is a block diagram illustrating in detail a memory controller 130, a DRAM memory array 140 and a data path 150 of a memory subsystem. Memory controller 130 and data path 150 are similar to memory controller 30 and data path 50 of FIG. 1 except that they do not include data strobe 55.

[0018] Memory controller 130 includes a plurality of flip-flops 31-36 coupled to a plurality of buffers 60-65. Each flip-flop 31-36 is coupled to a common clock signal, CLK 100. The D-input of each flip-flop 31-36 is coupled to additional circuitry within memory controller 130 (not shown).

[0019] DRAM memory array 140 includes two EDO DRAM memories, EDO DRAM A (DRAM 45) and EDO DRAM B (DRAM 46). DRAMs 45 and 46 each include a set of the plurality of DRAM DIMMs that comprise DRAM memory array 140. Flip-flops 31 and 32 generate and output a RAS signal. active low (RASA# 110) and a CAS signal, active low (CASA# 112), respectively, to DRAM 45. Flip-flop 33 (and other similar flip-flops, not shown, for each line) generate and output an address signal (Addr_A 114) that specifies the location to be accessed in DRAM 45. Flip-flops 34 and 35 output a RAS signal, active low (RASB# 116) and a CAS signal, active low (CASB# 118), respectively, to DRAM 46. Flip-flop 36 (and other similar flip-flops, not shown, for each line) output an address signal (Addr_B 120) that specifies the location to be accessed in DRAM 46.

[0020] DRAM memory array 140 outputs DRAM_Data 160. DRAM_Data 160 is a common data bus from DRAM memory array 140 to data path 150. Both sets of DRAM, DRAM 45 and DRAM 46, have one connection to each signal on DRAM_Data 160. This is done to reduce the number of pins required at data path 150. Connecting the data lines together limits how the two sets of DRAMs can be accessed so that accessing one does not interfere with accessing the other one. In one embodiment, DRAM Data 160 includes 72 data lines.

[0021] Data path 150 includes a flip-flop 51 for each line of DRAM_Data 160 coupled to DRAM_Data 160 through a buffer 66 and coupled to CLK 100. The output of flip-flop 51, Data 170, is the final captured data set that will be transmitted to the requesting device, usually one of the processors 20-23 in computer system 10.

[0022]FIG. 3 is a timing diagram of DRAM access to DRAM memory array 140 of FIG. 2. Access starts with a row address being applied to Addr_A 114 and RASA# 110 being asserted during time=3. RASA# 110 must be asserted during the entire memory access. Next, Addr_A 114 changes to the column address during time=6 and CASA# 112 is asserted during time=8. Some time after CASA# 112 is asserted (i.e., during time=8), DRAM_Data 160 will transition to an active state from the no driver or high-impedance state. This time is defined as tON and is specified by the DRAM manufacturer. After an additional time, tCAC 300, DRAM 45 is guaranteed to be driving valid data (during time=11). The data cannot be captured at data path 150, however, until an additional flight time delay has elapsed. The flight time is the time it takes the DRAMs to charge the wires or PCB traces in the system to their proper. valid levels and for the electrical wave-front to reach the pins of data path 150. After the data is captured in data path 150, RASA# 110 can be de-asserted (during time=12).

[0023] In high performance computer systems, memory access times and bandwidth are critical to overall system performance and sometimes extreme measures are taken to provide that performance. One common technique is to access more than one set of memory at a time to reduce the apparent access latency. In other words, if one location in memory can be accessed, and while that access is taking place, another can start being accessed, the second access latency penalty can be hidden. That is one reason why there are two sets of DRAM memories, DRAM 45 and 46, in DRAM memory array 140. While the access to DRAM 45 has been started by a set of sequences on the control signals of DRAM 45, a similar set of sequences on the control signals of DRAM 46 takes place to start access to DRAM 46. That is also why there are two sets of signals input to DRAM memory array 140. With two sets, each access can be started individually.

[0024] The timing diagram of FIG. 3 illustrates that the set of signals for DRAM 46 begin during time=4 and time=5. The RAS portion (RASB# 116) of the access can precede but memory controller 130 must wait before asserting the CAS signal (CASB# 118) as this would cause DRAM 46 to start outputting data on DRAM_Data 160 which would conflict with and corrupt the data from the first access. CASB# 118 is asserted during time=13 and the data is captured from DRAM 46 during time=16 and 17.

[0025] The minimum DRAM to DRAM access time in the timing diagram of FIG. 3 is measured from the first data from DRAM 45 being captured to the second data from DRAM 46 being captured. Two things must happen between the two accesses: the first DRAM (DRAM 45) must stop driving the common data bus, DRAM_Data 160 (which translates to memory controller 130 waiting a fixed number of clocks until starting the next access) and then the CAS# access time for the second request must be met.

[0026] In FIG. 3 the first access completes during time=12, and the rest of time=12 is used waiting for DRAM 45 to turn off and then the next CAS# access starts. The second access completes during time=17 with data being captured in data path 150. This results in 5 clocks as the minimum time from one access to the next and sets the minimum latency and the maximum bandwidth for the system shown in FIG. 2 without data strobe 55. In one embodiment of the present invention, 32 bytes are read with each memory access and the clock period is 10 ns. Five clock periods is 50 ns. Therefore the maximum sustained bandwidth is 32/50 ns=640 MB per second using the memory subsystem of FIG. 2 without data strobe 55.

[0027] The following timing equations apply to the memory subsystem of FIG. 2 without data strobe 55.

tCAC=tCOCAS+tFLIGHTCAS+tDEVICECAC+tDATAFLIGHT+tDSU.  (1)

[0028] Where tCAC is the CAS access time (tCAC 300 in FIG. 3), or the time it takes to access data from the falling edge of CAS (Max) and:

[0029] tCOCAS=Time from positive clock edge through the flip-flop and buffer of the memory controller;

[0030] tFLIGHTCAS=Time that the CAS signal takes to propagate to the DRAM devices (e.g., DRAMs 45 and 46). With a large amount of board routing, capacitance and connectors, this can become significant (e.g., 5-10 ns);

[0031] tDEVICECAC=Time it takes for the DRAM devices to access data from a CAS# assertion;

[0032] tDATAFLIGHT=Time that the data signals take to propagate to the data path device (e.g., data path 150). With a large amount of board routing, capacitance and connectors, this can become significant (e.g., 5-10 ns);

[0033] tDSU=Time required by the data path that data must arrive before a positive clock edge so that it is clocked in the device validly. Logic and buffers in the input stage of the data path can make this significant.

[0034] tCAC sets the minimum amount of time that the DRAMs can be accessed in the memory subsystem, rounded up to the next positive clock edge. So if tCAC is 35 ns then, for a system with a 10 ns clock period, the minimum access time would be four clocks.

tON=tCOCAS+tFLIGHTCAS+tDEVICEON,  (2)

[0035] where tDEVICEON is the time it takes for the DRAM device itself to detect CAS asserted and start outputting data. tON is the time from CAS assertion to the DRAMs driving data (min).

tOFF=tCOCAS+tFLIGHTCAS+tDEVICEOFF,  (3)

[0036] where tDEVICEOFF is the time it takes for the DRAM device to stop driving data. tOff is the time from RAS de-assertion to the DRAMS changing to high impedance (max).

[0037] tON and tOFF work in conjunction when accessing multiple rows or sets of DRAM devices coupled to the same data bus. If the minimum value of tON is greater than the maximum value of tOFF then the access from one device to the next can occur simultaneously. Typically, this is never the case. tON is normally near zero and tOFF is usually a large positive number somewhere around 10 ns. This means that the memory controller must wait nearly a full tOFF time before starting the access to the next row of DRAMS. This increases the latency as previously described. This wait time occurs during time=12 in FIG. 3.

[0038]FIG. 4 is a block diagram illustrating in more detail memory controller 30, DRAM memory array 40 and data path 50 of the memory subsystem of FIG. 1 in accordance with one embodiment of the present invention. Memory controller 30 is structurally similar to memory controller 130. However, memory controller 30 includes a flip-flop 38 coupled to a buffer 69 that generates data strobe 55 (also referred to as “LDSTB#” in FIGS. 4 and 5). Flip-flop 38 is also coupled to CLK 100. DRAM memory array 40 is structurally similar to DRAM memory array 140 of FIG. 2.

[0039] Data path 50 includes a latch 52. DRAM_Data 260, which is the output data bus from DRAM memory array 40, is coupled to buffer 66 and the input of latch 52. Data strobe 55 is coupled to the gate of latch 52. The output of latch 52 is coupled to the input of flip-flop 51. Flip-flop 51 is further coupled to CLK 100 and outputs data 270 to the requesting device.

[0040] As shown in FIG. 4, data strobe 55 is generated by the same clock (CLK 100) as CASA# 212 and CASB# 218. By providing an asynchronous signal that is synchronous with the main data access control signals, CAS# 212 and 218, the data can be captured at data path 50 before the next rising edge of the common clock. This allows the first access at DRAM 45 to be terminated one clock earlier and the next access at DRAM 46 to start one clock earlier than without data strobe 55.

[0041]FIG. 5 is a timing diagram of DRAM access to DRAM memory array 40 of FIG. 4. As in FIG. 3, access starts with a row address being applied to Addr_A 214 and RASA# 210 being asserted during time=3. Next, Addr_A 214 changes to the column address during time=6 and CASA# 212 is asserted during time=8.

[0042] During time=10, data strobe 55 is asserted. This causes data on DRAM_Data 260 to flow through latch 52. RASA# 210, CASA# 212 and data strobe 55 can then be de-asserted during time=11 because the de-assertion of data strobe 55 will cause the data flowing through latch 52 to be captured. The de-assertion of RASA# 210 will cause DRAM 45 to stop outputting data. The wait time during time=12 of FIG. 3 can then be eliminated and the next CAS# assertion (CASB# 218) can take place at time=12. This reduces the row to row access time from 5 clocks in FIG. 3 without data strobe 55 to 4 clocks with data strobe 55. The bandwidth increases from 640 MB/s to 800 MB/s with data strobe 55, which is a 25% increase.

[0043] The assertion of data strobe 55 is predictive with respect to the arrival of valid data. Since the assertion only opens the gate of latch 52, this is acceptable. The deassertion of data strobe 55 during time=11 is the edge that actually finalizes the captured data in between positive edges of the clock. After the data is captured, the setup time to flip-flop 51 that captures data internal to data path 50 must still be met.

[0044] This is easily implemented in a monolithic semiconductor device.

[0045] The following timing equation apply to the memory subsystem of FIG. 4 with data strobe 55.

tCAC=tCOCAS+tFLIGHTCAS−tCOLDSTB−tFLIGHTDSTB+tDEVICECAC+tDATAFLIGHT+tDSU.  (5)

[0046] Where:

[0047] tCOLDSTB=Time from positive clock edge until data strobe 55 appears at the device pins. Since data strobe 55 and CAS# are generated from the same device, using identical circuits, the tCO (i.e., the time delay due to the built-in capacitance of the traces) for each will be nearly identical in value;

[0048] tFLIGHTDSTB=Time that data strobe 55 takes to propagate to data path device 50. With a large amount of board routing, capacitance and connectors this can be significant but is almost always less than tFLIGHTCAS due to less routing and load.

[0049] In equation (5), tDSU changes slightly in value in comparison to the previous tDSU in equation 1 because it is now the time for data to setup to latch 52 with respect to data strobe 55.

[0050] As compared to tCAC 300 for the memory subsystem without data strobe 55, both tCOLDSTB and tFLIGHTDSTB are subtracted from the tCAC 500 with data strobe 55 because they are generated from the same device using the same clock and because it becomes the effective clock at data path 50. Therefore, the use of data strobe 55 decreases the value of tCAC 500 compared to tCAC 300 of FIG. 3. Data strobe 55 should be used as the gate for latch 52, not a clock for flip-flop 51.

[0051] As described, in the present invention data strobe 55 from memory controller 30 to data path 50 decreases the wait time between an access of DRAM 45 followed by an access of DRAM 46 because the CAS for the first access can be de-asserted earlier. This results in a decreased access time to DRAM memory array 40 regardless of the length of the traces from memory controller 30 to DRAM memory array 40.

[0052] Several embodiments of the present invention are specifically illustrated and/or described herein. However, it will be appreciated that modifications and variations of the present invention are covered by the above teachings and within the purview of the appended claims without departing from the spirit and intended scope of the invention. 

What is claimed is:
 1. A memory subsystem for a computer system comprising: a memory controller comprising a data strobe generator; a dynamic random access memory (DRAM) array coupled to said memory controller; and a data path coupled to said data strobe generator and said DRAM array.
 2. The memory subsystem of claim 1 , said memory controller further comprising a first and second address generator, a first and second row address strobe (RAS) generator and a first and second column address strobe (CAS) generator.
 3. The memory subsystem of claim 2 , wherein said DRAM array comprises: a first DRAM set coupled to said first address generator, said first RAS generator and said first CAS generator; a second DRAM set coupled to said second address generator, said second RAS generator and said second CAS generator; and a DRAM data output bus coupled to said first DRAM set and said second DRAM set.
 4. The memory subsystem of claim 3 , wherein said data path comprises: a latch having a first input coupled to said data strobe generator and having a second input coupled to said DRAM data output bus, and having an output; and a data path flip-flop having an input coupled to said latch output.
 5. The memory subsystem of claim 4 , further comprising a clock; wherein said data path flip-flop, said first and second address generator, said first and second RAS generator and said first and second CAS generator are coupled to said clock.
 6. The memory subsystem of claim 3 , wherein said memory controller accesses said first DRAM set, asserts and de-asserts said data strobe. and accesses said second DRAM set after de-asserting said data strobe.
 7. The memory subsystem of claim 1 , wherein said data path couples data retrieved from said DRAM array to a requesting device.
 8. The memory subsystem of claim 1 , wherein said memory controller receives requests for access to said DRAM array.
 9. A method of accessing a dynamic random access memory (DRAM) array comprising a first DRAM set, a second DRAM set, and a DRAM array output, said method comprising: (a) asserting a first column address strobe (CAS) to said first DRAM set; (b) asserting a data strobe to a data path coupled to said DRAM array output; (c) latching first data on said DRAM array output at the data path based on said data strobe; (d) de-asserting said data strobe and said first CAS; and (e) asserting a second CAS to said second DRAM set.
 10. The method of claim 9 . wherein said first data on said data path is valid while said data strobe is asserted.
 11. The method of claim 9 , further comprising; (f) asserting the data strobe a second time to the data path; and (g) latching second data on said DRAM array output at the data path.
 12. The method of claim 10 , wherein said first CAS is de-asserted on a next clock cycle after said data strobe is asserted.
 13. The method of claim 9 , further comprising: clocking said first data through a flip-flop on a next clock cycle after said data strobe is asserted.
 14. The method of claim 10 , further comprising: asserting a first row address strobe (RAS) to said first DRAM set; de-asserting the first RAS; and asserting a second RAS to said second DRAM set.
 15. The method of claim 14 , wherein the first CAS is de-asserted when the first RAS is de-asserted.
 16. A memory subsystem for a computer system comprising: a memory controller; a DRAM memory array coupled to said memory controller and comprising a first DRAM set, a second DRAM set, and a DRAM array output; and a data path coupled to said memory controller and said DRAM array output; wherein said memory controller comprises: means for asserting a first column address strobe (CAS) to said first DRAM set; means for asserting a data strobe to said data path means for latching first data on said DRAM array output at the data path based on said data strobe; means for de-asserting said data strobe and said first CAS; and means for asserting a second CAS to said second DRAM set.
 17. The memory subsystem of claim 16 , wherein said first data on said data path is valid while said data strobe is asserted.
 18. The memory subsystem of claim 16 , said memory controller further comprising; means for asserting the data strobe a second time to the data path; and means for latching second data on said DRAM array output at the data path.
 19. The memory subsystem of claim 16 , wherein said first CAS is de-asserted on a next clock cycle after said data strobe is asserted.
 20. The memory subsystem of claim 16 , said memory controller further comprising: means for clocking said first data through a flip-flop on a next clock cycle after said data strobe is asserted.
 21. The memory subsystem of claim 17 , said memory controller further comprising: means for asserting a first row address strobe (RAS) to said first DRAM set; means for de-asserting the first RAS; and means for asserting a second RAS to said second DRAM set.
 22. The memory subsystem of claim 21 , wherein the first CAS is de-asserted when the first RAS is de-asserted.
 23. A computer system comprising: a processor; a memory bus coupled to said processor; and a memory subsystem coupled to said memory bus, said memory subsystem comprising: a memory controller comprising a data strobe generator; a dynamic random access memory (DRAM) array coupled to said memory controller; and a data path coupled to said data strobe generator and said DRAM array.
 24. The computer system of claim 23 , said memory controller further comprising a first and second address generator, a first and second row address strobe (RAS) generator and a first and second column address strobe (CAS) generator.
 25. The computer system of claim 24 , wherein said DRAM array comprises: a first DRAM set coupled to said first address generator, said first RAS generator and said first CAS generator; a second DRAM set coupled to said second address generator, said second RAS generator and said second CAS generator; and a DRAM data output bus coupled to said first DRAM set and said second DRAM set.
 26. The computer system of claim 25 , wherein said data path comprises: a latch having a first input coupled to said data strobe generator and having a second input coupled to said DRAM data output bus, and having an output; and a data path flip-flop having an input coupled to said latch output.
 27. The computer system of claim 26 , further comprising a clock; wherein said data path flip-flop, said first and second address generator, said first and second RAS generator and said first and second CAS generator are coupled to said clock.
 28. The memory subsystem of claim 25 , wherein said memory controller accesses said first DRAM set, asserts and de-asserts said data strobe, and accesses said second DRAM set after de-asserting said data strobe. 